1. Field of the Invention
The present invention generally relates to image sensing devices and, more particularly, is directed to an image sensing device in which a transfer efficiency of a horizontal transfer unit is improved.
2. Description of the Prior Art
FIG. 1 shows a structure of a CCD (charge-coupled device) solid state image sensing device of, for example, an interline transfer system as an example of a solid state image sensing device. Referring to FIG. 1, an imager unit 3 comprises a plurality of light sensing units 1 which are arranged at the pixel units (picture element) in the vertical and horizontal directions in a two-dimensional array design. They store electric charges corresponding to a quantity of incident light. vertical shift register (vertical transfer unit) 2 is provided for transferring electric charges read out from these light sensing units 1 at every vertical column in the vertical direction. Electric charges of all pixels photoelectrically-converted by the light sensing units 1 are read out in a moment to the vertical shift registers 2 during one portion of the vertical blanking period. The electric charges transferred to the vertical shift registers 2 are transferred to a horizontal shift register (horizontal transfer unit) 4 by the amount corresponding to one scanning line during one portion of the horizontal blanking period. Electric charges of an amount corresponding to one scanning line are sequentially transferred by the horizontal shift register 4 to the horizontal direction. An output circuit unit 5 is provided at the final end portion of the horizontal shift register 4. This output circuit unit 5 is formed of a FDA (floating diffusion amplifier) or the like and outputs the electric charges photoelectrically-converted by the light sensing units 1 in the converted form of a voltage.
FIG. 2 shows in sectional form a structure of a transfer electrode unit of the horizontal shift register 4 in the CCD image sensing device. As is apparent from FIG. 2, each of a plurality of transfer electrodes 6 in the horizontal shift register 4 is constructed by an electrode pair formed of a storage (ST) gate electrode 7 and a transfer (TR) electrode 8 of a double layer structure made of polysilicon. These electrode pairs are driven in two-phase fashion by the application of two-phase transfer clocks H.phi.1 and H.phi.2 of the same phase.
FIG. 4 shows a potential diagram of the horizontal shift register 4 at a timing point t.sub.0 of FIG. 3. A potential difference .DELTA..phi.1 in FIG. 4 is generated by injecting P ions only to the transfer gate electrode 8 in an ion-imlantation technique. Thus electric charge amount Q.sub.H of the horizontal shift register 4 is determined, whereas .DELTA..phi.2 in FIG. 4 represents a potential difference between clocks of different phases. This potential difference .DELTA..phi.2 influences the transfer efficiency of the horizontal shift register 4. Further, (.DELTA..phi.1+.DELTA..phi.2) is determined by a peak value Ha of the transfer clocks H.phi.1 and H.phi.2 shown in a waveform diagram of FIG. 3.
Recently, it is to be appreciated that the peak value Ha of the transfer clocks H.phi.1 and H.phi.2 tends to decrease in accordance with the decrease of the level of voltage applied to the transfer electrode 6. Since the peak value Ha is decreased, a sufficient potential difference (.DELTA..phi.1+.DELTA..phi.2) cannot be obtained and it becomes impossible to obtain the potential difference .DELTA..phi.1 which can satisfy both the electric charge amount Q.sub.H and the transfer efficiency of the horizontal shift register 4. In other words, if the transfer efficiency of the horizontal shift register 4 is satisfied, then the peak value Ha of the transfer clock is lowered, resulting in the electric charge amount Q.sub.H of the horizontal shift register 4 being decreased.